1. Field of the Invention
The present invention relates to a decimation filter for analogue-digital conversion and to an interpolation filter for digital-analogue conversion, and in particular to rationalization of coefficient word length in an FIR filter.
2. Description of the Related Art
Conventionally, a decimation filter is used for A/D conversion, while an interpolation filter is used for D/A conversion. In particular, a decimation filter comprising 1/2x down sampling FIR filters in cascade connection and an interpolation filter comprising 2x over sampling FIR filters in cascade connection are commonly used.
FIG. 1 shows a structure of a standard FIR filter. As shown, a signal is sequentially supplied to a plurality of serially connected zxe2x88x921 delay units 1, which then sequentially create estimates based on the signal to respectively output delayed signals. The signals output from the respective zxe2x88x921 delay units 1 are supplied to their corresponding coefficient multipliers 2, where the signal is multiplied by respective predetermined coefficients a0, a1, . . . , before being supplied to a common adder 3. The adder 3 adds the signals, or delayed data, with predetermined weight. In the above, the adder 3 outputs filtering outputs, depending on a coefficient of the coefficient multiplier 2.
FIG. 2 shows an example of an interpolation filter, in which 2x over sampling FIR filters 4-1 to 4-3 are connected in a three-stage cascade relationship for conversion of digital data having 1 fs (sampling frequency) into digital data having 8 fs. This structure is often employed for conversion of digital data having 1 fs into digital data having 8 fs since it can be realized using a smaller hardware than a structure using an 8x over sampling FIR filter.
FIGS. 3 to 5 show example characteristics of a 4x interpolation filter comprising 2x over sampling FIR filters 4-1 to 4-2 in two-stage cascade connection. FIG. 3 relates to a characteristic of a first-stage FIR filter 4-1, FIG. 4 relates to a characteristic of a second-stage FIR filter 4-2, and FIG. 5 relates to the overall characteristic of the complete filter.
A coefficient word length of the first-stage FIR filter 4-1 is 16 bits and attenuation in an inhibition zone of the entire filter is xe2x88x9264.5 dB. Comprehensive characteristics of the complete filter are substantially determined based on the attenuation by the first-stage FIR filter. Any increase of attenuation in an inhibition zone of the first-stage FIR filter 4-1 requires proportional increase of the circuit size. It should, however, be noted that the attenuation in an inhibition zone of a second-stage FIR filter 4-2 can be increased without significantly increasing the circuit size.
FIG. 6 shows an example of a standard decimation filter comprising 1/2x down sampling FIR filters 5-1 to 5-3 arranged in a three-stage cascade connection for conversion of digital data having 8 fs into digital data having 1 fs. Filter characteristic of a 1/4 decimation filter comprising 1/2x down sampling FIR filters 5-1 to 5-2 in two-stage cascade connection is identical to that shown in FIGS. 3 and 4. Specifically, a filter characteristic of the third-stage FIR filter 5-3 is shown in FIG. 3, that of an FIR filter immediately before the third-stage FIR filter 5-3, that is, the second-stage FIR filter 5-2, is shown in FIG. 4, and that of the complete filter is shown in FIG. 5.
An output yj of a FIR-type digital filter is expressed as yj=xcexa3hixc2x7xi(i=i,n), wherein xi denotes an input, hi denotes a filter coefficient, and n denotes the number of taps. A FIR-type digital filter generally requires a multiplier. When no multiplier is employed, a parallel shift adder is used for time-dividing multiplication. In this case, increasing the attenuation in an inhibition zone requires that a coefficient word length of the filter and the number of taps both be increased. In other words, as described above, the circuit size of the first-stage FIR filter of an interpolation filter and that of the last-stage FIR filter of a decimation filter are significantly increased.
A longer filter coefficient word lengths lead to larger multiplier circuit sizes. When a parallel shift adder is used, a longer period of time is required to complete an operation. Therefore, in order to complete an operation within a predetermined period of time, modification must be made so as to include, for example, two or more parallel shift adders. This results in an increase in the size of the circuit.
According to the present invention, FIR filters are arranged in a cascade connection in which the last-stage FIR filter (for a decimation filter) or the first-stage FIR filter (for an interpolation filter) is arranged so as to have a shorter coefficient word length than that which is necessary to attain a desired characteristic. Although this results in insufficient attenuation in an inhibition zone of the first-or last-stage FIR filter, it is arranged such that regions with insufficient attenuation relative to the first- or last-stage FIR filter are caused near the Nyquist frequency, and that the Nyquist frequency and nearby frequencies are attenuated by a FIR filter immediate following or preceding the FIR filter, so that sufficient attenuation can be ensured over the entire filter.